A template-based methodology for efficient microprocessor and FPGA accelerator co-design

Embedded applications usually require Software/Hardware (SW/HW) designs to meet the hard timing constraints and the required design flexibility. Exhaustive exploration for SW/HW designs is a very time consuming task, while the adhoc approaches and the use of partially automatic tools usually lead to less efficient designs. To support a more efficient codesign process for FPGA platforms we propose a systematic methodology to map an application to SW/HW platform with a custom HW accelerator and a microprocessor core. The methodology mapping steps are expressed through parametric templates for the SW/HW Communication Organization, the Foreground (FG) Memory Management and the Data Path (DP) Mapping. Several performance-area tradeoff design Pareto points are produced by instantiating the templates. A real-time bioimaging application is mapped on a FPGA to evaluate the gains of our approach, i.e. 44,8% on performance compared with pure SW designs and 58% on area compared with pure HW designs

Area-throughput trade-offs for SHA-1 and SHA-256 hash functions’ pipelined designs

High-throughput designs of hash functions are strongly demanded due to the need for security in every transmitted packet of worldwide e-transactions. Thus, optimized and non-optimized pipelined architectures have been proposed raising, however, important questions. Which is the optimum number of the pipeline stages? Is it worth to develop optimized designs or could the same results be achieved by increasing only the pipeline stages of the non-optimized designs? The paper answers the above questions studying extensively many pipelined architectures of SHA-1 and SHA-256 hashes, implemented in FPGAs, in terms of throughput/area (T/A) factor. Also, guides for developing efficient security schemes designs are provided. Read More: https://www.worldscientific.com/doi/abs/10.1142/S021812661650032

On the Exploitation of a High-throughput SHA-256 FPGA Design for HMAC

High-throughput and area-efficient designs of hash functions and corresponding mechanisms for Message Authentication Codes (MACs) are in high demand due to new security protocols that have arisen and call for security services in every transmitted data packet. For instance, IPv6 incorporates the IPSec protocol for secure data transmission. However, the IPSec's performance bottleneck is the HMAC mechanism which is responsible for authenticating the transmitted data. HMAC's performance bottleneck in its turn is the underlying hash function. In this article a high-throughput and small-size SHA-256 hash function FPGA design and the corresponding HMAC FPGA design is presented. Advanced optimization techniques have been deployed leading to a SHA-256 hashing core which performs more than 30% better, compared to the next better design. This improvement is achieved both in terms of throughput as well as in terms of throughput/area cost factor. It is the first reported SHA-256 hashing core that exceeds 11Gbps (after place and route in Xilinx Virtex 6 board)

Integration of a concurrent signature monitoring mechanism in a system-on-a-chip

In this work, an IP infrastructure is presented that provides concurrent signature monitoring to the designed System-on-a-Chip (SoC). Such mechanisms ensure application code consistency and research focus integration inside high performance processor cores. A low-cost but very effective approach is offered, which has been successfully integrated in a prototype targeting safety critical applications. The advantages of the integration of this simple unit in a SoC and its characteristics are also presented. © 2007 IEEE.ST, Atmel,Altran Technologies, Alter

Case study and application of pre-computation technique for hashing cores aiming at high-throughput implementations

Hash functions are forming a special family of cryptographic algorithms, which are applied wherever message integrity and authentication issues are critical. Implementations of these functions are cryptographic primitives to the most widely used cryptographic schemes and security protocols such as SET, PKI, IPSec and VPN's. As time passes it seems that all these applications call for higher throughput due to their rapid acceptance by the market. In this work a new technique is presented for increasing frequency and throughput of all widely used hash functions - and those that will be used in the future- hash functions such as MD-5, SHA-1, RIPEMD (all versions), SHA-256, SHA-384, and SHA-512 etc. Comparing to conventional pipelined implementations of hash functions the proposed pre-computation technique leads to a 40%-25% higher throughput

Novel technique for high-throughput and power efficient cryptographic primitives

Most of internet applications incorporate a security layer in which a hash function is found. These applications are addressing to more and more clients and thus the corresponding server accepts a great number of service requests. In order to indulge these requests the security schemes must have a high-throughput. Furthermore, due to the tendency of the market to minimize devices' size and increase their autonomy to make them portable, power issues have also to be considered as long as the client-side is concerned. In this work the parallelism (or partial unrolling) technique is presented for increasing frequency and throughput of all widely used hash functions - and those that will be used in the future- hash functions such as MD-5, SHA-1, RIPEMD (all versions), SHA-256, SHA-384, and SHA-512 etc. The proposed parallelism technique leads to a 33%- 50% higher throughput comparing to the most competitive implementations and to much lower power dissipation